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eASIC Implements SynTest's Tools for Its Single-Mask Configurable IP Core to Allow Efficient Testability
SANTA CLARA, Calif.--(BUSINESS WIRE)--March 19, 2001--IP/SoC
Conference--eASIC® Corporation today announced that the company has
implemented SynTest ATPG (Automatic Test Pattern Generator) tools for
its eASICore(TM), a high-performance and high-density single-mask
configurable core. These tools will allow eASIC users to improve
testability and fault coverage, resulting in reduced defect levels and
tester time. eASIC customers can use the SynTest DFT tools,
Turbo-Scan-ATPG(TM) and TurboBIST-Memory(TM), to improve their
design's testability.
eASICore supports SynTest's TurboBIST for embedded memory testing
as well as its tools for generating design dependent test pattern for
manufacturing. Due to eASIC's special architecture features and the
re-programmability capability, the number of test vectors is reduced
significantly. For a typical ASIC design, a user can expect more than
60% reduction in the number of manufacturing test vectors required to
achieve 98% test coverage.
``We are pleased to have in place this partnership with SynTest and
jointly develop the eASICore testing capabilities in order to deliver
greater value to our customers,'' Zvi Or-Bach eASIC President and CEO.
``The need to support highly effective testing tools is becoming more
important as design complexity increases dramatically and development
cycle pressure arises. SynTest's tools fit very well in the standard
ASIC flow offered for eASICore implementation.''
L.-T. Wang, SynTest president, noted, ``eASIC has superior
technology for the embedded programmable logic market and is one of
our first partners addressing this market. Their eASICore customers
have the advantage of using our full scan and memory BIST products to
make their designs more testable and reduce their tester costs.''
About eASIC
eASIC Corporation is pioneering a breakthrough approach of
embedded configurable ASIC cores for System-on-Chip designs. This
configurable ASIC core, called eASICore, offers high performance and
density with ease-of-design, rapid time-to-market and low design
development cost. eASIC Corporation is a privately held company based
in San Jose, California. Part of its R&D activity is performed by its
wholly owned design subsidiary in Romania.
About SynTest
SynTest Technologies, Inc., develops and markets DFT, logic and
memory BIST synthesis, boundary scan, ATPG and fault simulation
software tools and offers consulting services throughout the world to
semiconductor companies, ASIC designers and test groups. SynTest has
offices in Korea, Taiwan and the USA and distribution partners in
Canada, Israel, France, Italy, the UK, Japan and Singapore.
Contact:
eASIC Corporation
Tsipi Landen, 408/264-7128
tsipi@easic.com
www.eASIC.com
or
ValleyPR
Georgia Marszalek, 650/345-7477
georgia@valleypr.com
www.syntest.com
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